In an asynchronous digital logic system, the various input, intermediate, and output signals do not occur in a clocked relationship with respect to one another. In a data processing system having an asynchronous bus and employing a dynamic RAM memory certain timing errors are likely to occur as a result of a lower priority RAM refresh request occurring just prior to a higher priority memory access request. It is known that dynamic RAM memories require periodic refreshing to maintain the data which is stored in them. Prior art prioritizing circuits have been unable to eliminate timing errors occurring when a refresh request occurs at approximately the same time as a memory access request. Such timing errors may severely affect the reliability of the RAM memory module.
For example, if a refresh request occurs immediately before an access request, the system priority logic may generate a brief refresh grant signal prior to generating an access grant signal. Consequently, the memory module may attempt a refresh operation and, before conclusion of the refresh operation, also attempt a memory access operation. As a consequence neither operation may be successfully performed.
It is therefore desirable to eliminate timing errors arising from closely occurring memory access and memory refresh request signals in an asynchronous data processing system employing a dynamic RAM memory module in order to improve the reliability of such system.